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cy7c09269v/79v/89v cy7c09369v/89v 3.3 v 16 k / 32 k / 64 k 16 / 18 synchronous dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-06056 rev. *i revised august 1, 2012 3.3 v 16 k / 32 k / 64 k 16 / 18 synchronous dual-port static ram features true dual-ported memory cells that allow simultaneous access of the same memory location six flow through/pipelined devices: ? 16 k 16 / 18 organization (cy7c09269v/369v) ? 32 k 16 organization (cy7c09279v) ? 64 k 16 / 18 organization (cy7c09289v/389v) three modes: ? flow through ? pipelined ? burst pipelined output mode on both ports allows fast 100 mhz operation 0.35 micron cmos for optimum speed and power high speed clock to data access: 7.5 [1] , 9, 12 ns (max) 3.3 v low operating power: ? active = 115 ma (typical) ? standby = 10 ? a (typical) fully synchronous interface for easier operation burst counters increment addresses internally: ? shorten cycle times ? minimize bus noise ? supported in flow through and pipelined modes dual chip enables easy depth expansion upper and lower byte controls for bus matching automatic power down commercial and industrial temperature ranges pb-free 100-pin tqfp package available r/ w l 1 0 0/1 ce 0l ce 1l lb l oe l ub l 1b 0/1 0b 1a 0a ba ft /pipe l i/o 8/9l ?i/o 15/17l i/o 0l ?i/o 7/8l i/o control counter/ address register decode a 0l ?a 13/14/15l clk l ads l cnten l cntrst l true dual-ported ram array r/ w r 1 0 0/1 ce 0r ce 1r lb r oe r ub r 1b 0/1 0b 1a 0a b a ft /pipe r i/o control counter/ address register decode 14/15/16 8/9 8/9 i/o 8/9r ?i/o 15/17r i/o 0r ?i/o 7/8r a 0r ?a 13/14/15r clk r ads r cnten r cntrst r 14/15/16 8/9 8/9 [2] [3] [2] [3] [4] [4] logic block diagram notes 1. see figure 4 on page 8 for load conditions. 2. i/o 8 ?i/o 15 for 16 devices; i/o 9 ?i/o 17 for 18 devices. 3. i/o 0 ?i/o 7 for 16 devices. i/o 0 ?i/o 8 for 18 devices. 4. a 0 ?a 13 for 16k; a 0 ?a 14 for 32k; a 0 ?a 15 for 64k devices.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 2 of 22 contents pin configurations ........................................................... 3 selection guide ................................................................ 5 pin definitions .................................................................. 5 functional description ..................................................... 6 maximum ratings ............................................................. 7 operating range ............................................................... 7 electrical characteristics ................................................. 7 capacitance ...................................................................... 7 ac test loads and waveforms ....................................... 8 switching characteristics ................................................ 9 switching waveforms .................................................... 10 read/write and enable operation ................................. 17 address counter control operation ............................. 17 ordering information ...................................................... 18 16 k 16 3.3 v synchronous dual-port sram ........ 18 32 k 16 3.3 v synchronous dual-port sram ........ 18 16 k 18 3.3 v synchronous dual-port sram ........ 18 64 k 18 3.3 v synchronous dual-port sram ........ 18 ordering code definitions ..... .................................... 19 package diagrams .......................................................... 19 acronyms ........................................................................ 20 document conventions ................................................. 20 units of measure ....................................................... 20 document history page ................................................. 21 sales, solutions, and legal information ...................... 22 worldwide sales and design s upport ......... .............. 22 products .................................................................... 22 psoc solutions ......................................................... 22
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 3 of 22 pin configurations figure 1. 100-pin tqfp (top view) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 a9r a10r a11r a12r a13r a14r ubr nc lbr ce1r cntrstr oer ft /piper nc a15r gnd r/wr gnd i/o15r i/o14r i/o13r i/o12r i/o11r i/o10r ce0r 58 57 56 55 54 53 52 51 cy7c09279v (32 k 16) cy7c09269v (16 k 16) a9l a10l a11l a12l a13l a14l ubl nc lbl ce1l cntrstl oel ft /pipel nc a15l vcc r/wl gnd i/o15l i/o14l i/o13l i/o12l i/o11l i/o10l ce0l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 a8l a7l a6l a5l a4l a3l clkl a1l cntenl gnd adsr a0r a1r a0l a2l clkr cntenr a2r a3r a4r a5r a6r a7r a8r adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 i/o10r i/o9r i/o8r i/o7r vcc i/o6r i/o1r i/o4r i/o2r gnd i/o0l i/o2l i/o3l i/o3r i/o5r i/o1l gnd i/o4l i/o5l i/o6l i/o7l vcc i/o8l i/o9l i/o0r 33 32 31 30 29 28 27 26 cy7c09289v (64 k 16) [5] [6] [7] [7] [5] [6] notes 5. this pin is nc for cy7c09269v. 6. this pin is nc for cy7c09269v and cy7c09279v. 7. for cy7c09269v and cy7c09279v, pin #18 connected to v cc is pin compatible to an idt 5 v 16 pipelined device; connecting pin #18 and #58 to gnd is pin compatible to an idt 5 v 16 flow through device.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 4 of 22 figure 2. 100-pin tqfp (top view) pin configurations (continued) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 a8r a9r a10r a11r a12r a13r ce0r a15r ubr cntrstr r/wr ft /piper i/o17r lbr a14r gnd oer gnd i/o16r i/o15r i/o14r i/o13r i/o12r i/o11r ce1r 58 57 56 55 54 53 52 51 cy7c09369v (16 k 18) a9l a10l a11l a12l a13l a14l ce1l lbl ce0l r/wl oel i/o17l i/o16l ubl a15l vcc ft /pipel gnd i/o15l i/o14l i/o13l i/o12l i/o11l i/o10l cntrstl 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 a8l a7l a6l a5l a4l a3l clkl a1l cntenl gnd gnd cntenr a0r a0l a2l adsr clkr a1r a2r a3r a4r a5r a6r a7r adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 i/o10r i/o9r i/o8r i/o7r vcc i/o6r i/01r i/o4r i/o2r gnd i/o0l i/o2l i/o3l i/o3r i/o5r i/o1l gnd i/o4l i/o5l i/o6l i/o7l vcc i/o8l i/o9l i/o0r 33 32 31 30 29 28 27 26 cy7c09389v (64 k 18) [8] [9] [8] [9] notes 8. this pin is nc for cy7c09369v. 9. this pin is nc for cy7c09369v.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 5 of 22 selection guide specifications cy7c09269v/79v/89v cy7c09369v/89v -7 [10] cy7c09269v/79v/89v cy7c09369v/89v -9 cy7c09269v/79v/89v cy7c09369v/89v -12 f max2 (mhz) (pipelined) 83 67 50 max. access time (ns) (clock to data, pipelined) 7.5 9 12 typical operating current i cc (ma) 155 135 115 typical standby current for i sb1 (ma) (both ports ttl level) 25 20 20 typical standby current for i sb3 ( ? a) (both ports cmos level) 10 10 10 pin definitions left port right port description a 0l ?a 15l a 0r ?a 15r address inputs (a 0 ?a 14 for 32k, a 0 ?a 13 for 16k devices). ads l ads r address strobe input. used as an address qualifier. this signal must be asserted low to access the part using an externally supplied address. asse rting this signal low also loads the burst counter with the address present on the address pins. ce 0l , ce 1l ce 0r ,ce 1r chip enable input. to select either the le ft or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 ? v il and ce 1 ?? v ih ). clk l clk r clock signal. this input can be free running or strobed. maximum clock input rate is f max . cnten l cnten r counter enable input. asserting this signal low increments the burst address counter of its respective port on each rising edge of clk. cnten is disabled if ads or cntrst are asserted low. cntrst l cntrst r counter reset input. asserting this signal low resets the burst address counter of its respective port to zero. cntrst is not disabled by asserting ads or cnten . i/o 0l ?i/o 17l i/o 0r ?i/o 17r data bus input/output (i/o 0 ?i/o 15 for 16 devices). lb l lb r lower byte select input . asserting this signal low enables read and write operations to the lower byte. (i/o 0 ?i/o 8 for 18, i/o 0 ?i/o 7 for 16) of the memory array. for read operations both the lb and oe signals must be asserted to drive output data on the lower byte of the data pins. ub l ub r upper byte select input. same function as lb , but to the upper byte (i/o 8/9l ?i/o 15/17l ). oe l oe r output enable input. this signal must be asserted low to enable the i/o data pins during read operations. r/w l r/w r read/write enable input . this signal is asserted low to write to the dual port memory array. for read operations, assert this pin high. ft /pipe l ft /pipe r flow through/pipelined select input. for flow through mode operation, assert this pin low. for pipelined mode operation, assert this pin high. gnd ground input . nc no connect . v cc power input . note 10. see figure 4 on page 8 for load conditions.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 6 of 22 functional description the cy7c09269v/79v/89v and cy7c09369v/89v are high speed 3.3 v synchronous cmos 16 k, 32 k, and 64 k 16 and 16 k and 64 k 18 dual-port static rams. two ports are provided, permitting independent, simultaneous access for reads and writes to an y location in memory [11] . registers on control, address, and data lines allow for minimal setup and hold times. in pipelined output mode, data is registered for decreased cycle time and clock to data valid t cd2 = 7.5 ns [12] (pipelined). flow through mode can also be used to bypass the pipelined output register to eliminate access latency. in flow through mode, data is available t cd1 = 18 ns after the address is clocked into the device. pipelined output or flow through mode is selected through the ft /pipe pin. each port contains a burst count er on the input address register. the internal write pulse width is independent of the low to high transition of the clock signal. the internal write pulse is self timed to allow the shortest possible cycle times. a high on ce 0 or low on ce 1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. the use of multiple chip enables enables easier banking of multiple chips for depth expansion configurations. in the pipelined mode, one cycle is required with ce 0 low and ce 1 high to reactivate the outputs. counter enable inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast interleaved memory applications. a port?s burst counter is loaded with the port?s address strobe (ads ). when the port?s count enable (cnten ) is asserted, the address counter increments on each low to high transition of that port?s clock signal. this reads/writes one word from or into each successive address location, until cnten is deasserted. the counter can address the entire memory array and loop back to the start. counter reset (cntrst ) is used to reset the burst counter. all parts are available in 100-pin thin quad plastic flatpack (tqfp) packages. notes 11. when writing simultaneously to the same location, the final value cannot be guaranteed. 12. see figure 4 on page 8 for load conditions.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 7 of 22 maximum ratings exceeding maximum ratings [13] may impair the useful life of the device. these user guidelines are not tested. storage temperature ???????????????????????????????????? 65 ? c to +150 c ambient temperature with power applied ???????????????????????????????????????????????? 55 ? c to +125 ? c supply voltage to ground potential ????????????? ? 0.5 v to +4.6 v dc voltage applied to outputs in high z state ???????????????????????????????????????? ? 0.5 v to v cc + 0.5 v dc input voltage ???????????????????????????????????? ? 0.5 v to v cc + 0.5 v output current into outputs (low) ............................ 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ............ > 1100 v latch up current .................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.3 v ? 300 mv industrial ?40 c to +85 c 3.3 v ? 300 mv electrical characteristics over the operating range parameter description cy7c09269v/79v/89v cy7c09369v/89v unit -7 [14] -9 -12 min typ max min typ max min typ max v oh output high voltage (v cc = min, l oh = ?4.0 ma) 2.4 ? ? 2.4 ? ? 2.4 ? ? v v ol output low voltage (v cc = min, l oh = +4.0 ma) ? ? 0.4 ? ? 0.4 ? ? 0.4 v v ih input high voltage 2.0 ? ? 2.0 ? ? 2.0 ? ? v v il input low voltage ? ? 0.8 ? ? 0.8 ? ? 0.8 v i oz output leakage current ?10 ? 10 ?10 ? 10 ?10 ? 10 ? a i cc operating current (v cc = max, i out = 0 ma) outputs disabled commercial ? 155 275 ? 135 230 ? 115 180 ma industrial ? 275 390 ? 185 300 ? ? ? ma i sb1 standby current (both ports ttl level) [15] ce l & ce r ? v ih , f = f max commercial?2585?2075?2070ma industrial ? 85 120 ? 35 85 ? ? ? ma i sb2 standby current (one port ttl level) [15] ce l | ce r ? v ih , f = f max commercial ? 105 165 ? 95 155 ? 85 140 ma industrial ? 165 210 ? 105 165 ? ? ? ma i sb3 standby current (both ports cmos level) [15] ce l & ce r ? v cc ? 0.2 v, f = 0 commercial ? 10 250 ? 10 250 ? 10 250 ? a industrial ? 10 250 ? 10 250 ? ? ? ? a i sb4 standby current (one port cmos level) [15] ce l | ce r ? v ih , f = f max commercial ? 95 125 ? 85 115 ? 75 100 ma industrial ? 125 170 ? 95 125 ? ? ? ma capacitance parameter [16] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 10 pf c out output capacitance 10 pf notes 13. the voltage on any input or i/o pin can not exceed the power pin during power up. 14. see figure 4 on page 8 for load conditions. 15. ce l and ce r are internal signals. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 ? v il and ce 1 ?? v ih ). 16. tested initially and after any design or process changes that may affect these parameters.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 8 of 22 ac test loads and waveforms figure 3. ac test loads and waveforms figure 4. ac test loads (applicable to -7 only) [17] (a) normal load (load 1) r1 = 590 ? 3.3 v output r2 = 435 ? c= 30 pf v th = 1.4 v output c= 30 pf (b) thvenin equivalent (load 1) (c) three-state delay(load 2) r1 = 590 ? r2 = 435 ? 3.3 v output c= 5pf r th =250 ? (used for t cklz , t olz , and t ohz including scope and jig) v th = 1.4 v output c (a) load 1 (-7 only) r = 50 ? z 0 = 50 ? 3.0 v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses ? ? 0.00 0.1 0 0.20 0.30 0.40 0.50 0.60 5 3 0 3 5 2 0 2 5 1 0 1 (b) load derating curve capacitance (pf) (ns) for all -7 access times note 17. test conditions: c = 10 pf.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 9 of 22 switching characteristics over the operating range parameter description cy7c09269v/79v/89v cy7c09369v/89v unit -7 [18] -9 -12 min max min max min max f max1 f max flow through ? 45 ? 40 ? 33 mhz f max2 f max pipelined ?83?67?50mhz t cyc1 clock cycle time - flow through 22 ? 25 ? 30 ? ns t cyc2 clock cycle time - pipelined 12?15?20?ns t ch1 clock high time - flow through 7.5 ? 12 ? 12 ? ns t cl1 clock low time - flow through 7.5 ? 12 ? 12 ? ns t ch2 clock high time - pipelined 5?6?8?ns t cl2 clock low time - pipelined 5?6?8?ns t r clock rise time ?3?3?3ns t f clock fall time ?3?3?3ns t sa address set-up time 4?4?4?ns t ha address hold time 0?1?1?ns t sc chip enable setup time 4 ? 4 ? 4 ? ns t hc chip enable hold time 0 ? 1 ? 1 ? ns t sw r/w set-up time 4?4?4?ns t hw r/w hold time 0?1?1?ns t sd input data setup time 4?4?4?ns t hd input data hold time 0?1?1?ns t sad ads set-up time 4?4?4?ns t had ads hold time 0?1?1?ns t scn cnten setup time 4.5 ? 5 ? 5 ? ns t hcn cnten hold time 0?1?1?ns t srst cntrst setup time 4?4?4?ns t hrst cntrst hold time 0?1?1?ns t oe output enable to data valid ?9?10?12ns t olz [19, 20] oe to low z 2?2?2?ns t ohz [19, 20] oe to high z 171717ns t cd1 clock to data valid - flow through ? 18 ? 20 ? 25 ns t cd2 clock to data valid - pipelined ? 7.5 ? 9 ? 12 ns t dc data output hold after clock high 2 ? 2 ? 2 ? ns t ckhz [19, 20] clock high to output high z 2 9 2 9 2 9 ns t cklz [19, 20] clock high to output low z 2 ? 2 ? 2 ? ns port to port delays t cwdd write port clock high to read data delay ? 35 ? 40 ? 40 ns t ccs clock to clock setup time ? 10 ? 15 ? 15 ns notes 18. see figure 4 on page 8 for load conditions. 19. test conditions used are load 2. 20. this parameter is guaranteed by design, but it is not production tested.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 10 of 22 switching waveforms figure 5. read cycle for flow through output (ft /pipe = v il ) [21, 22, 23, 24] figure 6. read cycle for pipelined operation (ft /pipe = v ih ) [21, 22, 23, 24] t ch1 t cl1 t cyc1 t sc t hc t dc t ohz t oe t sc t hc t sw t hw t sa t ha t cd1 t ckhz t dc t olz t cklz a n a n+1 a n+2 a n+3 q n q n+1 q n+2 clk ce 0 ce 1 r/w address data out oe t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce 0 ce 1 r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency notes 21. oe is asynchronously controlled; all other i nputs are synchronous to the rising clock edge. 22. ads = v il , cnten and cntrst = v ih . 23. the output is disabled (high impedance state) by ce 0 =v ih or ce 1 = v il following the next rising edge of the clock. 24. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 11 of 22 figure 7. bank select pipelined read [25, 26] figure 8. left port write to flow through right port read [27, 28, 29, 30] switching waveforms (continued) d 3 d 1 d 0 d 2 a 0 a 1 a 2 a 3 a 4 a 5 d 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk l address (b1) ce 0(b1) data out(b2) data out(b1) address (b2) ce 0(b2) t sa t ha t sw t hw t sd t hd match valid t ccs t sw t hw t dc t cwdd t cd1 match t sa t ha match no match no valid valid t dc t cd1 clk l r/ w l address l data inl address r data outr clk r r/ w r notes 25. in this depth expansion example, b1 represents bank #1 and b2 is bank #2; each bank consists of one cypress dual-port device from this datasheet. address (b1) = address (b2) . 26. ub , lb , oe and ads = v il ; ce 1(b1) , ce 1(b2) , r/w , cnten , and cntrst = v ih . 27. the same waveforms apply for a right port write to flow through left port read. 28. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and cntrst = v ih . 29. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 30. it t ccs ? maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs >maximum specified, then data is not valid until t ccs + t cd1 . t cwdd does not apply in this case.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 12 of 22 figure 9. pipelined read-to-write-to-read (oe = v il ) [31, 32, 33, 34] figure 10. pipelined read-to-write-to-read (oe controlled) [31, 32, 33, 34] switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd t cklz t cd2 no operation write read read clk ce 0 ce 1 r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+3 a n+4 q n q n+3 t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 t cklz t cd2 q n q n+4 clk ce 0 ce 1 r/w address data in data out oe notes 31. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. 32. output state (high, low, or high impedance) is determined by the previous cycle control signals. 33. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 34. during ?no operation?, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrit y.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 13 of 22 figure 11. flow through read-to-write-to-read (oe = v il ) [35, 36, 37, 38] figure 12. flow throug h read-to-write-to-read (oe controlled) [35, 36, 37, 38, 39] switching waveforms (continued) t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t sw t hw t sd t hd a n a n+1 a n+2 a n+2 a n+3 a n+4 d n+2 q n q n+1 q n+3 t cd1 t cd1 t dc t ckhz t cd1 t cd1 t cklz t dc read no operation write read clk ce 0 ce 1 address r/w data in data out q n t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t cd1 t dc t ohz read a n a n+1 a n+2 a n+3 a n+4 a n+5 d n+2 d n+3 t sw t hw t sd t hd t cd1 t cd1 t cklz t dc q n+4 t oe write read clk ce 0 ce 1 address r/w data in data out oe notes 35. ads = v il , cnten and cntrst = v ih . 36. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. 37. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 38. during ?no operation?, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrit y. 39. output state (high, low, or high impedance) is determined by the previous cycle control signals.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 14 of 22 figure 13. pipelined read with address counter advance [40] figure 14. flow through read with address counter advance [40] switching waveforms (continued) counter hold read with counter t sa t ha t sad t had t scn t hcn t ch2 t cl2 t cyc2 t sad t had t scn t hcn q x-1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address clk address ads data out cnten a n t ch1 t cl1 t cyc1 t sa t ha t sad t had t scn t hcn q x q n q n+1 q n+2 q n+3 a n t sad t had t scn t hcn t dc t cd1 counter hold read with counter read external address read with counter clk address ads data out cnten note 40. ce 0 and oe = v il ; ce 1 , r/w and cntrst = v ih .
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 15 of 22 figure 15. write with address counter advance (flow through or pipelined outputs) [41, 42] switching waveforms (continued) notes 41. ce 0 , ub , lb , and r/w = v il ; ce 1 and cntrst = v ih . 42. the ?internal address? is equal to the ?external address? when ads = v il and equals the counter output when ads = v ih .
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 16 of 22 figure 16. counter reset (pipelined outputs) [43, 44, 45, 46] switching waveforms (continued) t ch2 t cl2 t cyc2 clk address internal cnten ads data in address cntrst r/w data out q 0 q 1 q n d 0 a x 01a n a n+1 t sad t had t scn t hcn t srst t hrst t sd t hd t sw t hw a n a n+1 t sa t ha counter reset write address 0 read address 0 read address 1 read address n notes 43. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. 44. output state (high, low, or high impedance) is determined by the previous cycle control signals. 45. ce 0 , ub , and lb = v il ; ce 1 = v ih . 46. no dead cycle exists during counter reset. a read or write cycle ma y be coincidental with the counter reset.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 17 of 22 read/write and enable operation the read/write and enable operation is described as follows. [47, 48, 49] inputs outputs operation oe clk ce 0 ce 1 r/w i/o 0 ? i/o 17 x h x x high z deselected [50] x x l x high z deselected [50] x l h l d in write l l h h d out read [51] h x l h x high z outputs disabled address counter c ontrol operation the address counter control operat ion is described as follows. [47, 52, 53, 54] address previous address clk ads cnten cntrst i/o mode operation x x x x l d out(0) reset counter reset to address 0 a n x l x h d out(n) load address load into counter x a n h h h d out(n) hold external address blocked ? counter disabled x a n h l h d out(n+1) increment counter enabled ? internal address generation notes 47. ?x? = ?don?t care?, ?h? = v ih , ?l? = v il . 48. ads , cnten , cntrst = ?don?t care?. 49. oe is an asynchronous input signal. 50. when ce changes state in the pipelined mode, deselection and read happen in the following clock cycle. 51. ads = v il , cnten and cntrst = v ih . 52. ce 0 and oe = v il ; ce 1 and r/w = v ih . 53. data shown for flow through mode; pipelined mode output is delayed by one cycle. 54. counter operation is independent of ce 0 and ce 1 .
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 18 of 22 ordering information 16 k 16 3.3 v synchronous dual-port sram speed (ns) ordering code package diagram package type operating range 7.5 [55] cy7c09269v-7axc 51-85048 100-pin tqfp (pb-free) commercial 9 cy7c09269v-9axc 51-85048 100-pin tqfp (pb-free) commercial 12 cy7c09269v-12axc 51-85048 100-pin tqfp (pb-free) commercial 32 k 16 3.3 v synchronous dual-port sram speed (ns) ordering code package diagram package type operating range 7.5 [55] cy7c09279v-7axc 51-85048 100-pin tqfp (pb-free) commercial 12 cy7c09279v-12axc 51-85048 100-pin tqfp (pb-free) commercial 64 k 16 3.3 v synchronous dual-port sram speed (ns) ordering code package diagram package type operating range 9 cy7c09289v-9axc 51-85048 100-pin tqfp (pb-free) commercial cy7c09289v-9axi 51-85048 100-pin tqfp (pb-free) industrial 12 CY7C09289V-12AXC 51-85048 100-pin tqfp (pb-free) commercial 16 k 18 3.3 v synchronous dual-port sram speed (ns) ordering code package diagram package type operating range 9 cy7c09369v-9axc 51-85048 100-pin tqfp (pb-free) commercial 12 cy7c09369v-12axc 51-85048 100-pin tqfp (pb-free) commercial 64 k 18 3.3 v synchronous dual-port sram speed (ns) ordering code package diagram package type operating range 7.5 [55] cy7c09389v-7axc 51-85048 100-pin tqfp (pb-free) commercial 9 cy7c09389v-9ai 51-85048 100-pin tqfp industrial note 55. see page 6 for load conditions.
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 19 of 22 ordering code definitions temperature range: x = c or i c = commercial; i = industrial x = pb-free (rohs compliant) package type: a = 100-pin tqfp speed grade: xx = 7.5 ns or 9 ns or 12 ns v = 3.3 v x9 = depth: x = 6 or 7 or 8 6 = 16k; 7 = 32k; 8 = 64k width: x = 2 or 3 2 = 16; 3 = 18 09 = sync technology code: c = cmos marketing code: 7 = dual port sram company id: cy = cypress 7 cy 09 - xx x x x v x x9 c package diagrams figure 17. 100-pin tqfp (14 14 1. 4 mm) a100sa package outline, 51-85048 51-85048 *g
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 20 of 22 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mm millimeter mv millivolt ns nanosecond ? ohm % percent pf picofarad vvolt
cy7c09269v/79v/89v cy7c09369v/89v document number: 38-06056 rev. *i page 21 of 22 document history page document title: cy7c09269v/79v/89v/cy7c 09369v/89v, 3.3 v 16 k / 32 k / 64 k 16 / 18 synchronous dual-port static ram document number: 38-06056 revision ecn submission date orig. of change description of change ** 110215 12/18/01 szv change from spec number: 38-00668 to 38-06056 *a 122306 12/27/02 rbi power up requirements added to maximum ratings information *b 344354 see ecn pcx added pb-free part ordering information *c 2678221 03/25/2009 vkn / aesa added cy7c09379v-12axct part. updated 51-85048 to *c. *d 2896210 03/22/2010 rame updated ordering information . updated package diagrams . *e 3111417 12/15/2010 admu updated ordering information . added ordering code definitions . *f 3124048 12/30/2010 admu no technical updates. *g 3352110 08/23/2011 admu updated features (removed cy7c09379v information and also removed -6 speed bin information). updated pin configurations (removed cy7c09379v information). updated selection guide (removed cy7c09379v information and also removed -6 speed bin information). updated functional description (removed cy7c09379v information). updated electrical characteristics (removed cy7c09379v information and also removed -6 speed bin information). updated ac test loads and waveforms (removed -6 speed bin information). updated switching characteristics (removed cy7c09379v information and also removed -6 speed bin information). updated ordering information (removed part cy7c09279v-7ac). updated package diagrams . added acronyms and units of measure . updated in new template. *h 3402091 10/12/2011 admu updated ordering information (removed pruned part cy7c09289v-9ai). updated package diagrams . *i 3680923 08/01/2012 admu / smch updated pin configurations (updated figure 2 ). updated switching characteristics (changed name of parameter from t ckz to t ckhz , changed name of parameter from t ckz to t cklz in the next corresponding row). updated switching waveforms (updated figure 15 ). updated address counter control operation . updated ordering information (removed pruned part cy7c09289v-9ac). updated package diagrams (spec 51-85048 (changed revision from *e to *g)).
document number: 38-06056 rev. *i revised august 1, 2012 page 22 of 22 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c09269v/79v/89v cy7c09369v/89v ? cypress semiconductor corporation, 2001-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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